This application claims priority based on Korean Patent Application No. 2003-9359, filed on Feb. 14, 2003, in the Korean Intellectual Property Office.
1. Field of the Invention
The present invention relates to the structure of a contact and a wire line of a semiconductor device, and more particularly, to a method for forming a bit line by a damascene process using a hard mask formed from storage node contacts in a DRAM having a bit line formed on a capacitor.
2. Discussion of the Related Art
As semiconductor devices become highly integrated, a multi-layered interconnection structure has been widely used. The interconnection structure includes wire lines and contacts. For example, a semiconductor device, such as a DRAM, includes a semiconductor substrate in which elements, such as a transistor, are formed, a wire line, such as a bit line, is electrically connected to a contact, and a capacitor is formed on the bit line. In this case, in order to connect the capacitor to the semiconductor device electrically, a capacitor contact (or storage node contact) is separated from the bit line and passes beside the bit line.
In general, in order to form a bit line and a capacitor thereover, a capacitor over bit line (COB) structure is formed by forming a storage node contact that passes beside the bit line and is electrically connected to a lower semiconductor substrate. However, as the design rule of semiconductor devices, in particular, DRAMs are reduced severely, it becomes very difficult to form a COB structure.
In a typical COB structure, after a bit line is formed, a storage node contact is formed. In this case, in order to obtain a sufficient process margin, spacers are formed at sides of the bit line, and a hard mask formed of silicon nitride (Si3N4) is formed on the bit line. The spacers and the hard mask are used so that a storage node contact is formed by a self aligned contact (SAC) process. As a result, the hard mask should be formed to a large thickness on the bit line, so as to perform the SAC process. However, as the design rule of a semiconductor device is reduced, it becomes very difficult to etch a hard mask formed of silicon nitride (Si3N4) having a large thickness.
As the design rule of the semiconductor device is reduced, an ArF process has been performed essentially during a photolithography process. In the ArF process, the thickness of a photoresist layer is reduced gradually. As such, it is very difficult to form a photoresist pattern having a sufficient thickness to pattern a hard mask formed of silicon nitride (Si3N4) having a large thickness. Thus, it becomes very difficult to form a hard mask having a sufficient thickness to be used in the SAC process on a bit line.
In addition, when a thick hard mask is used in the SAC process, the height of a bit line stack increases. As such, gap filling cannot be easily performed when filling an interlevel dielectric (ILD) layer between bit lines. That is, a high aspect ratio occurs between bit lines, such that it is difficult to perform gap filling. In particular, as the design rule of the semiconductor device is reduced to less than 90 nm, it becomes difficult to perform gap filling.
In order to form a bit line having a fine critical dimension (CD) as the design rule of the semiconductor device is reduced, attempts to form a bit line by a damascene process after a storage node contact (i.e., capacitor contact) is formed are disclosed in U.S. Patent Publication No. US2002/0022315 A1 (published on Feb. 21, 2002). A method for forming a bit line to be aligned in a capacitor contact by the damascene process can be used even when the design rule of the semiconductor devices is reduced rapidly, by obtaining a larger process margin.
According to the above-described Patent Publication, the upper portion of a capacitor contact has a protective cap and is protected from the damascene process, which is performed by a trench standard lithography process for a bit line.
However, as the design rule of the semiconductor device is reduced rapidly, it becomes difficult to form a photoresist pattern for patterning a trench to a sufficient thickness to be used as an etch mask during an etch process for forming a trench, as described above. In order to pattern a trench reliably, when a photoresist pattern is used as an etch mask, the photoresist pattern should be formed to a sufficient large thickness. However, when the design rule of the semiconductor device is reduced to less than 90 nm, it is very difficult to form a photoresist pattern to a sufficient thickness. In particular, it is very difficult to pattern a photoresist layer to a very large thickness during a photolithography process using an ArF illumination system when the design rule of the semiconductor device is less than 90 nm. In addition, when the photoresist pattern is formed to a large thickness, it is quite probable that the photoresist pattern will collapse.
In addition, as described above, a process for forming a silicon nitride layer as a protective cap on a capacitor contact is accompanied by processes of recessing, depositing, and additionally etching a capacitor contact. As such, a semiconductor device manufacturing process becomes complicated, thereby reducing the productivity of the process.
Accordingly, a need exists for a simplified semiconductor device manufacturing process in which a patterning process for forming a trench to be used in a damascene process is more reliably performed.